Antenna-in-Package Design Based on Wafer-Level Packaging With Through Silicon Via Technology

Abstract

In this paper, a CPW-fed antenna-in-package (AiP) operating at millimeter wave (mmWave) based on a wafer-level packaging technology with through silicon via (TSV) interconnections is proposed, designed, and measured. The designed antenna consists of two-stacked high-resistivity silicon (HRSi) substrates. One is the bottom HRSi substrate with thickness of 750 μm, which carries the slot radiator and the CPW feeding. The other one is the top HRSi substrate with thickness of 200 μm carrying a patch, which is placed on the radiating element for antenna gain and efficiency improvement. The vertical interconnects in this structure are designed using the TSVs built on a HRSi wafer, which are designed to carry the radio frequency (RF) signals up to mmWave. RF path transitions are carefully designed to minimize the return loss within 10 dB in the frequency band of concern. The designed AiP is fabricated and measured, and the measured results basically match the simulation results. It is demonstrated that a wider bandwidth and less-sensitive input impedance versus the fabrication process accuracy are obtained with the designed structure in this paper. The measured results show the radiation in the broadside of the structure with gain around 2.4 dBi from 76 to 93 GHz.