Abstract

Background: Systematic/stochastic pattern defects affect the production yield of integrated circuits (IC) containing trillions of 10-nm level features. Aim: We detect pattern anomalies/defects from images obtained from scanning electron microscopes (SEM) for random/arbitrary IC patterns without using design data. Approach: We decompose SEM images into small sub-images and apply an identical autoencoder to each of them to detect anomalies. The astronomical varieties in random IC patterns are reduced into limited varieties in elementary patterns, which are coded onto limited dimension latent vectors in autoencoder. The discrepancy between autoencoder input and output represents a deviation of local pattern shapes from ideal or allowed ones and is used as an index of anomaly. Results: A wide variety of anomalies/defects are detected in regular and random IC patterns fabricated by extreme ultra-violet lithography without prior knowledge about anomalies at a high signal-to-noise ratio within a time shorter than the typical image acquisition time of SEMs. They include missing/necking in holes/trenches, collapsing/breaking in lines, various local pattern distortion/deformation, and tiny particles. Frequency and spatial distributions of the discrepancy index are sensitive to process changes and can be used for visualizing the sign or causes of anomalies. Conclusions: The method is effective for inspecting memory and random logic ICs with high-speed SEMs.

Highlights

  • The densities of integrated circuits (IC) are increasing with continuously shrinking circuit patterns, which is achieved by the introduction of EUV lithography and/or multiple patterning technologies

  • A wide variety of anomalies/defects are detected in regular and random IC patterns fabricated by extreme ultra-violet lithography without prior knowledge about anomalies at a high signal-to-noise ratio within a time shorter than the typical image acquisition time of scanning electron microscopes (SEM)

  • The method is effective for inspecting memory and random logic ICs with highspeed SEMs

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Summary

Introduction

The densities of integrated circuits (IC) are increasing with continuously shrinking circuit patterns, which is achieved by the introduction of EUV lithography and/or multiple patterning technologies. The following two types of defects are becoming major concerns; systematic defects are generated at particular spots in design patterns where the process windows are narrow (aka hot-spots or weak-spots).[1] Stochastic defects are generated randomly in EUV resist patterns due to photon shot noise and discrete/probabilistic natures of materials, and their probability exponentially increases with decreasing feature size.[2] The sizes of both types of defects are typically smaller than minimum circuit feature size and they are highly sensitive to process conditions, are generated by unexpected variations in process conditions. Systematic/stochastic pattern defects affect the production yield of integrated circuits (IC) containing trillions of 10-nm level features

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