Anomalous output characteristics shrinkage in STI-LDMOS transistor after repetitive I-V scanning measurements

Abstract

The STI-LDMOS (shallow trench isolation-lateral double-diffused MOS) is widely used in the power ICs by merits of high breakdown voltage, low on-resistance and compatibility with standard CMOS process. The performance of STI-LDMOS, the reliability should be taken into consideration because it works in high current density and high electric field state chronically. In this work, an anomalous output I-V characteristics shrinkage phenomenon has been found in the STI-LDMOS after repetitive I-V scanning measurements. The shrinking mechanism is attributed to the generated interface state at the STI corner near the source side with the help of the TCAD simulations and charge pumping (CP) experiments. Based on the shrinking mechanism, the one-sided stepped STI-LDMOS is proposed to solve this problem. The results show that the proposed device can alleviate effectively the high impact ionization rates at the damaged STI corner.