Abstract

The influence of dry-etching (D/E) damage during the source/drain (S/D) electrode etching process on the electrical properties of a bottom-gate In-Ga-Zn-O thin-film transistor (TFT) was investigated by varying the thickness of the etch-stop layer (ESL). For a thicker ESL of 200 nm, electrical properties of the TFTs with S/D electrodes formed by dry and wet-etching were comparable. However, an anomalous increase in apparent field-effect mobility ( $\mu _{\mathrm {FE}})$ was observed from the TFT with the S/D-D/E process with thinner ESL. Experimental and device simulation results clarified that the current flow line in the channel and an effective channel length were strongly influenced by the carrier density of the low-resistive region formed at a back-channel region, which was induced by the S/D-D/E damage through ESL.

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