Anomalous failure in low-voltage p-chanel power MOSFETs during the intrinsic diode recovery time

Abstract

This paper studies and analyzes the root causes of anomalous failures of low-voltage p-channel power MOSFETs during the intrinsic diode recovery time in dV/dt test. In particular, the dV/dt characterization test is described and, afterwards, specific electrical tests are provided to explain the root causes. From the electrical results point of view, the dV/dt slew rate does not involve an intrinsic bipolar transistor turn-on, as usually assumed in these kinds of failure. Instead, a gate oxide degradation occurs causing the device to fail as a result of dV/dt repetitive events. Such kinds of gate oxide degradation were observed measuring the threshold voltage degradation after an established dV/dt train of impulses till the failure occured. Afterwards, the same train of impulses was implemented on a new series of samples, changing the circuit and, in particular, inserting a resistor in the gate electrode. In this test, no failures were observed, even if several repetitive trains of impulses were supplied.