Anomalous drain-induced barrier lowering in short channel NMOS devices at 77 K

Abstract

Anomalous results on drain-induced barrier lowering (DIBL) in short channel NMOS devices at 77K are presented. It was found that for devices with channel lengths 0.7 and 1.3 μm, the DIBL measured by the change in gate voltage induced by a unit change in drain voltage at a fixed drain current was worse at 77K than at 300K. However, for devices that were either shorter than 0.7 μm or longer than 1.3 μm, DIBL was improved at 77K compared with 300K. The experimental results were in good agreement with the numerical calculations using MINIMOS 4.0.