Anomalous drain voltage dependence in bias temperature instability measurements on high-κ field effect transistors

Abstract

We find that changes in threshold voltage induced by negative bias temperature stressing of p-channel field effect transistors with HfSiON gate dielectrics are modulated by the drain voltage, in measurements wherein the drain current is measured during stressing. This effect is not observed in SiO 2 gate devices. Short channel effects are excluded as explanations, leading us to conclude that positive charge in the dielectric stack is laterally mobile and is conducted out of the insulator via the drain. Further, a simple qualitative model of charging kinetics allows us to extract the density of interface states as a function of time, and shows that these defects build in time, reaching numbers on the order of 10 11 cm −2 after hundreds of seconds.