Angle Effects in High Current Ion Implantation

Abstract

Previous studies conducted on batch high current implanters with 130 nm devices[1] have shown the importance of implant angle during source‐drain (SD) and source‐drain extension (SDE) implants. For these implants, errors in implant angle lead to device asymmetry and this device asymmetry has been cited as a reason for requiring single wafer high current implanters[2]. The sensitivity of device performance to angle is increasing as devices shrink. For current anneal technologies, angle effects are more importance in NMOS, due to the lower diffusion of arsenic. However, the importance of implant angle in PMOS is expected to increase as diffusionless anneals are adopted. In this paper we report on angle effects in single wafer high current ion implantation, for the improvement of the characteristics of MOSFETs integrated into Systems‐on‐a‐Chip (SoCs) of 65 nm or beyond. The single wafer high current implanter and its angle measurement and control system will be described. A comparison of the implanter’s angle measurements to device data will be presented.