Abstract

The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes unreliable at voltages below about 700 mV due to process variations and decreased device drive strength [2]. In order to achieve reliable operation, new bitcell topologies and assist methods have been proposed. This paper provides a comparison of four different bitcell topologies using read and write VMIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4–13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV. Using assist methods can reduce both read and write VMIN by 100 mV over the unassisted test case.

Highlights

  • As mobile devices become heavily energy constrained, the need for ultra low power circuits has emerged

  • To compare bitcell topologies for subthreshold and to test assist features, we implemented a test chip that was fabricated in MITLL 180 nm FDSOI

  • In this paper we present a novel asymmetric Schmitt Trigger (ST) bitcell which uses single ended reading to achieve

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Summary

Introduction

As mobile devices become heavily energy constrained, the need for ultra low power circuits has emerged. In order for the minimum operating voltage (VMIN) of SRAMs to enter the sub-threshold regime, more robust bitcell designs or assist methods must be used. One possible solution to this problem is to design a more robust bitcell topology capable of larger read and write margins. The downside to this strategy is that adding more transistors to the bitcell increases the total area of the array. The second strategy is to use various assist methods [4,5,6,7,8,9,10,11,12,13] to make the cell easier to read and write This method results in a smaller area overhead and may require multiple voltage sources.

Introduction of Sub-Threshold Bitcell Topologies
Write Assist Methods
Read Assist Methods
Results
Conclusions

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