Analyzing instruction prefetching techniques via a cache performance model: effectiveness and limitations

Abstract

Instruction prefetching methods are analyzed using a cache performance model. Improvement in performance achieved by using an instruction prefetching method is classified into two factors: the number of cache misses reduced by prefetching and the average amount of miss penalty reduced by successful prefetches. Conventional instruction prefetching methods are analyzed based on these two factors. Results show that the amount of miss penalty reduced by successful prefetches, called prefetch efficiency, is more crucial in obtaining a significant improvement in performance than the number of cache misses reduced by a given prefetching method. The effectiveness and limitations of conventional methods used to increase prefetch efficiency are examined using the analytical model and simulation. The analysis reveals that any effective instruction prefetching technique should be designed by utilizing the architectural characteristics of the underlying memory system as an important fundamental direction to achieve significant performance improvement required for future high performance systems.