Analyzing Binary Tree based Topology Configuration for Energy Efficient Multicore Architectures

Abstract

Modern computer architectures are moving towards domain-specific designs of processors. ARM-based processors domi-nate the embedded domain due to their compact and energy-efficient design. x86 processors have higher computing capabilities but at the cost of high energy consumption. This work tries to improve the Network-on-Chip design of x86 processors to have an energy-efficient Chip Multi-Processor configuration with similar computing power. Network-on-Chip is a significant part of modern computer architecture. It helps to efficiently navigate on-chip traffic on current Chip Multi-Processors where the number of cores is increasing rapidly. The topology of a Network-on-Chip significantly impacts system performance as it directly affects the network bandwidth and the area of the system. Therefore, Network-on-Chip topology affects the system's execution time, area, and energy consumption. This work proposes a novel topology to improve performance in terms of energy consumption and execution time, and affects L1D miss rate of the considered specification with few benchmark programs. The proposed topology is inspired from the traditional binary tree topology and tries to overcome its shortcomings to improve the system performance. The experiment results suggest that the proposed topology improves system performance on applications belonging to domains that are suited for embedded class processors.