Abstract

Solving a two-dimensional (2-D) Poisson equation in the channel region, we have developed models for short channel n/sup +/-p/sup +/ double-gate SOI MOSFETs, and showed how to design a device with a decreased gate length, suppressing short channel threshold voltage shift /spl Delta/Vth and subthreshold swing (S-swing) degradation. According to our model, we can design a 0.05 /spl mu/m L/sub G/ device of which threshold voltage is 0.2 V, /spl Delta/Vth is 25 mV, and S-swing is 65 mV/decade with a 3-nm-thick gate oxide and 12-nm-thick SOI.

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