Abstract
A surface potential-based compact model for independent dual gate (IDG) amorphous In-Ga-Zn-O thin-film transistors (IDG a-IGZO TFTs) is proposed here. The transport theories of percolation conduction, trap-limited conduction (TLC), and variable range hopping (VRH) in extended and localized states are first considered simultaneously via Schroder method, obtaining a physical description of the transport mechanism under different conditions of temperature and gate voltage. Moreover, a single formulation of front and back surface potentials which is valid and extremely accurate in all operation regimes is developed. Based on the transport theories and surface potentials, the complete compact model is developed and verified using both numerical simulation and experiment with an excellent agreement, and the threshold compensation effect is also included. Finally, the compact model is coded in Verilog-A, and implemented in a vendor CAD environment, which suggested that the proposed model can be successfully applied to circuit design.
Highlights
O N ACCOUNT of the extremely low leakage current and the possibility of low-temperature fabrication, amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) are under active research and development in the circuit application such as flexible display, memory, and 3-D integration [1]–[3]
The independent dual gate (IDG) a-IGZO TFTs have become the key choice in the industry due to its controllability of turn-on voltage and enhancement of ON/OFF-current ratio [4]–[6]
The trap-limited conduction (TLC)-dominated mobility-related parameter T0 was extracted as 410 K, Nt in our model has been extracted from the subthreshold swing (SS) of the experimental transfer curves as 1018 cm−3, andVFB1 and VFB2 were set to −0.2 V and −0.5 V, respectively
Summary
O N ACCOUNT of the extremely low leakage current and the possibility of low-temperature fabrication, amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) are under active research and development in the circuit application such as flexible display, memory, and 3-D integration [1]–[3]. To further effectively evaluate circuit performance, it is significant to have an accurate compact model describing the physical device behavior. Due to the amorphous disordered structure, charge transport in a-IGZO exhibits complex behavior, which brings difficulty in calculating the surface potentials, and the latter is the key issue in the modeling of IDG transistors [7], [8]. The surface potential-based completely compact model of IDG a-IGZO TFT considering amorphous structure and charge transport is still lacking. We develop a physics-based compact model for IDG a-IGZO TFT considering both traps and free electrons in an analytical way. With the combination of percolation conduction, trap-limited conduction (TLC), variable range hopping (VRH) for transport mechanism, and a new capacitance calculation method for dual-gate transistors, the model accurately replicates the experimental data. The compact model is evaluated for circuit design in SPICE
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
