Abstract
This paper addresses the problem of cell placement which is considered crucial for layout quality. Based on the combined analytical and partitioning strategy successfully applied in the GORDIAN placement tool, we discuss the consequences of using linear or quadratic objective functions. By joining the linear objective with an efficient quadratic programming approach, and by applying a refined iterative partitioning scheme, we obtain placements of excellent quality. The effect of a quadratic and a linear objective function on the chip area after final routing is demonstrated for benchmark circuits and other circuits with up to 21 000 cells.
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