Analytical Modeling and Simulation Based Investigation of Advanced TFET Architecture

Abstract

In this paper we have demonstrated a 50 nm n-channel gate stack undoped drain double gate tunneling field effect transistor (DG-TFET), for which the simulation shows significant improvements compared with gate stack double gate tunneling field effect transistor. The curves have been checked for both negative and positive gate bias state and also to check for the ON-State and am-bipolar state performance of the device architecture. Further, the variation of Work Function has also been implemented in the model and the results produced have been validated against the simulated data generated through ATLAS. Simultaneously, exhaustive simulation study regarding the performance of the proposed architecture i.e. the p-i-n DG TFET with undoped drain has been done. The results of the gate stack undoped drain double gate tunneling field effect transistor (DG-TFET) architecture are compared with the conventional p-i-n TFET. The better potential profile, energy band profile, drain current value and CGG value for the proposed device architecture make it suitable candidate for future level switching circuits because of compressed output current on negative bias.