Abstract
In the present work, the impact of Negative Capacitance (NC) effect of ferroelectric materials has been studied on Elliptical Gate All Around Junctionless Transistors by incorporating these materials as gate insulator. Landau Devonshire theory and parabolic potential approximation has been used to develop an analytical model to obtain various electrical parameters like surface potential, gate capacitance, subthreshold slope etc. The effect of varying aspect ratio (AR) has been incorporated in the model by obtaining effective radius depending on lengths of major and minor axes. Using the developed model a comparative analysis has been done for devices with two different ferroelectric materials, PZT and SBT, to investigate the feasibility of these materials for integration into future CMOS technology. It has been observed that for different aspect ratios, the device exhibits gain > 1 which also leads to point subthreshold swing value as low as 9mV/dec for SBT and 11mV/dec for PZT for a small range of applied bias, thereby, signifying suitability of such devices for sub-60mV/dec, low power applications.
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