Analytical model of internal heat transfer of a power chip with through silicon via

Abstract

Three-dimensional integration is considered as one of the effective methods that continue the rapid development of microelectronic technology for More than Moore. Through Silicon Via (TSV), which is used to connect signals on different layers, is the critical factor of three-dimensional integration technology. Because of its lower thermal resistance, TSV is also beneficial for heat dissipation. In order to verify the feasibility of using TSV as an internal nested heat dissipation structure in three-dimensional systems, an analytical model of internal heat transfer of a power chip with TSV was proposed. Based on the proposed theoretical model, the thermal resistance of the vertical silicon path and the TSV path is 32.4K/W and 5.34K/W, respectively. It is proved to be feasible that using TSV for internal heat dissipation of a power chip. The simulated results of the thermal resistance on the two paths are nearly consistent with the theoretical ones. So, the analytical model of the heat transfer is correct and validated.