Analytical Expressions for Doped Polycrystalline Silicon Thin-Film Transistors in Above-Threshold Regime Consistent With Pao–Sah Model Considering Trapped Charge Effect

Abstract

Based on a depleted and trapped charge analysis, threshold-voltage-based analytical drain current and capacitance expressions are presented in the above-threshold regime for doped polycrystalline silicon thin-film transistors assuming a symmetric exponential distribution (V-shaped) density of trap states (DOS) within the energy gap. A parameter β is proposed by considering “the trapped charge effect,” i.e., the increase of trapped charge with increasing gate voltage. The relationship between the parameter β and the DOS is clarified. In particular, the expressions are consistent with the Pao-Sah model. Good agreements are achieved by comparing this paper with experimental data.