Analytical Delay Modeling of On-Chip Hybrid RGLC Interconnect

Abstract

In modern IC chips, on chip interconnects plays a dominant role because of the device parasitic's. Several analytical and mathematical models are used for the interconnect analysis for delay reduction. But with the technology scaling towards nanometers, interconnect length is increasing exponentially. So, more accurate and efficient techniques for interconnect analysis are essential to reduce the propagation delays and increase the overall circuit performance in-terms of speed. Here a new interconnect scheme based on the transmission line model is proposed. This interconnect scheme has a resistance and conductance at the input, output and a lossless T-type LC network between them. Closed form delay model of interconnect is developed, which is a third order approximation to achieve better accuracy and less delays. The lumped delay models such as RC, RLC and RLGC are compared with the proposed model of interconnect for performance analysis in-terms of propagation delays and average power. The comparison analysis have shown that the proposed model of interconnect has less transients, average and propagation delays when compared to the other delay models.