Abstract
3D chip stacking is considered known to overcome conventional 2D-IC issues, using through silicon vias to ensure vertical signal transmission. From any point source, embedded or not, we calculate the impedance spread out; our ultimate goal will to study substrate noise via impedance field method. For this, our approach is twofold: a compact Green function or a Transmission Line Model over a multi-layered substrate is derived by solving Poisson’s equation analytically. The Discrete Cosine Transform (DCT) and its variations are used for rapid evaluation. Using this technique, the substrate coupling and loss in IC’s can be analyzed. We implement our algorithm in MATLAB; it permits to extract impedances between any pair of embedded contacts. Comparisons are performed using finite element methods.
Highlights
As the complexity of mixed digital-analog designs increases and the area of the current technologies decreases, substrate noise coupling in integrated circuits becomes a significant consideration in the design
The Discrete Cosine Transform (DCT) and its variations are used for rapid evaluation
We implement our algorithm in MATLAB; it permits to extract impedances between any pair of embedded contacts
Summary
As the complexity of mixed digital-analog designs increases and the area of the current technologies decreases, substrate noise coupling in integrated circuits becomes a significant consideration in the design. Nanotechnology and the development of semiconductor technology enable designers to integrate multiple systems into a single chip, in 2D (planar), and in 3D (in the bulk). This design technology reduces cost, while improves performance and makes the system on chip possible. A key study in a recent paper of ourselves [4] comes from the fact that, when, for instance, the MOS bulk-electrode is floating, the bulk potential becomes a function of the substrate perturbations and this affects, for instance, the value of the MOS threshold voltage which in turn varies the MOS drain current. The CMOS devices are implemented using the standard layers of the 0.35 μm BiCMOS ST Microelectronics-like technology and with threshold voltages of 0.65 V for nMOS and –0.6 V for pMOS
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