Abstract
This paper deals with investigation and fabrication of 4H-SiC MOSFETs with a high-k dielectric close to ZrSiO4. We are looking for the optimal stochiometry in order to obtain full benefits of its large bandgap, a k value higher than that of SiO2, thermodynamic stability on SiC, a good interface quality and process compatibility with SiC technology. Several Si/Zr ratios have been tested with the purpose of obtaining the most favorable dielectric configuration. The first test devices have been manufactured successfully with a stack gate dielectric consisting of a thin SiO2 interlayer and a ZrxSiyOz (theoretical Si/Z=0.7) layer on top.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
