Analysis of Within-Die Complementary Metal–Oxide–Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM

Abstract

Process-related variations are becoming a major concern for complementary metal–oxide–semiconductor (CMOS) technologies as the transistor size is scaled down. Hence, it is necessary to characterize the within-die (WID) and die-to-die (D2D) variations to establish a design methodology for the correct operation of ICs in the presence of such variations. Here, we have analyzed the stage-delay variation in ring oscillator arrays, fabricated in 180 nm CMOS technology, with large stage numbers and the possibility of flexible replacement for all ring oscillator stages. These allow an experimental analysis of the two-dimensional (2D) properties of the WID variation over the 1.69×1.59 mm2 area covered by the ring oscillators. Our results show that the measured variation data over this large area is still mainly of a Gaussian nature. Simulation of the delay stages of these ring oscillator arrays using the compact Hiroshima University STARC (Semiconductor Technology Academic Research Center) insulated gate field effect transistor (IGFET) Model (HiSIM) and some of the measurement data suggest that a systematic variation component, which does not change the Gaussian nature of the overall measurement data, may be present in the vertical direction of the ring oscillator array.