Analysis of wire bond and metallization degradation mechanisms in DMOS power transistors stressed under thermal overload conditions

Abstract

This paper reports about investigations concerning the degradation of the power metallization and wire bonds of smart power devices repeatedly stressed under cyclic thermal overload conditions. The fatigue of the interface between power metallization and bond wire finally leads to device failure (Drain-Source short circuit or open). Evaluation of experimental data revealed that for life time prediction a modified Coffin-Manson Equation describing time to failure as a function ofthermal as well as electrical stress parameters is applicable. Electrical and physical analysis of stressed devices is presented. Possible failure mechanisms of the DMOS silicon device are discussed.