Abstract
TCAD process and device simulations are used to gain physical understanding for the integration of laserannealed junctions into a 28 nm high-k/metal gate first process flow. Spike-RTA (Rapid Thermal Annealing) scaling used for transient enhanced diffusion (TED) suppression and shallow extension formation is investigated. In order to overcome the performance loss due to a reduced RTA, laser anneal (LSA) is introduced after Spike-RTA to form highly activated and ultra shallow junctions (USJ). In this work, the impact of different annealing conditions on the performance of NMOS and PMOS devices is investigated in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation.
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