Analysis of the ZTC-Point for Vertically Stacked Nanosheet pMOS Devices

Abstract

This paper shows an experimental analysis of the zero-temperature coefficient (ZTC) bias point of vertically stacked gate-all-around nanosheet pMOS devices (GAA-NS) for different channel lengths (L), in linear and saturation regions. The gate voltage at ZTC point (V ZTC ) experimental results are compared with the values obtained by analytical model (CM-ZTC model) in order to evaluate the behavior of the ZTC of the GAA-NS pMOS transistors. The comparison between the data from the CM-ZTC model and the experimental values resulted a difference smaller than 7% when operating in linear region, which means that the behavior of GAA-NS in ZTC point can be well described through the mobility degradation and threshold voltage shift basic models like in planar fully depleted SOI devices. However, in saturation region the difference increases substantially due to the high series resistance, and in case of 28 nm channel devices, due to the short-channel effect (SCE), which is not considered in the analytical model. But the experimental V ZTC in saturation region does not change too much (|V ZTZ | ≅ 0.75V with standard deviation ≅ 0.06V) for all studied devices (from 200 nm down to 28 nm channel lengths) which means that the GAA-NS is a trusted device for analog circuits biased at ZTC point.