Analysis of the quasi-saturation behavior considering the drain-to-source voltage and cell-spacing effects for a vertical DMOS power transistor

Abstract

This paper reports an analysis of the quasi-saturation behavior considering the drain-to-source voltage ( V DS) and cell-spacing effects for a vertical DMOS power transistor. Considering the unique electron distribution in the substrate, a V DS dependent quasi-saturation analytical model has been developed. As verified by the PISCES results, the analytical model provides an explanation of the cell-spacing-dependent quasi-saturation behavior in a DMOS device.