Analysis of the mobility behavior of MOS2 2D FETs

Abstract

In this work we analyze the behavior of 2D FETs, with channel length greater than the mean free path, and using MOCVD or CVD deposition method for the deposition of the 2D semiconductor layer, with different dielectric materials and EOTs. We show that transfer, output and conductance characteristics can be modeled with precision, considering the hopping transport mechanism as the predominant one, similarly to amorphous or polycrystalline TFTs. It was also observed that for the devices with channel length above one micrometer, mobility increased with the gate voltage as a power law. For channel lengths of 1 µm and 100 nm, mobility decreased with voltage, which in this case, can be attributed to other extrinsic effects, as the presence of high series resistance at the drain and source, which becomes more important as the channel length reduces, modifying its behavior with gate voltage.