Analysis of the Junction Properties of CdS/CdTe Devices in Substrate and Superstrate Configurations

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The best efficiency of CdS/CdTe devices fabricated in the substrate configuration reported to date is about 8%, which is about half the 17.3% reported for the conventional superstrate configuration. The performance of substrate devices is affected by lower open-circuit voltage (Voc), about 700 mV, and low fill factor (FF), which indicates that these devices are primarily limited by non-ideal junction properties and possibly by the ohmic contact to CdTe. In our study of the junction properties of superstrate devices, we show that lower-Voc devices ( 800 mV, the junction is between an n-type, Te-rich CdSTe alloy with a bandgap of 1.45 eV and p-type CdTe with a bandgap of 1.5 eV. Because the crystal structure of both the Te-rich alloy and the CdTe is cubic zinc blende, and the lattice mismatch between the two is minimal, the device in this case can be considered a quasi-homojunction. These higher-Voc devices are therefore affected less by the highmore » charged defect density at the hetero-interface, which lies outside of the depletion region. We present analysis of the junction properties of our recent and improved substrate-configuration devices with Voc well in excess of 800 mV, FF approaching 60%, and efficiencies around 10%. We also compare devices fabricated in both the substrate and superstrate configurations and with comparable Voc in the range of 700 to more than 800 mV. Photoluminescence (PL) and temperature-dependent PL, current density-voltage and quantum efficiency analysis, and modulated reflectance measurements are used to study device properties.« less