Abstract
The reduction in current ability accompanied by the hump phenomenon in oxide semiconductor thin-film transistors to which high DC voltages and AC drive voltages are applied has not been studied extensively, although it is a significant bottleneck in the manufacture of integrated circuits. Here, we report on the origin of the hump and current drop in reliability tests caused by the degradation in the oxide semiconductor during a circuit driving test. The hump phenomenon and current drop according to two different driving stresses were verified. Through a numerical computational simulation, we confirmed that this issue can be caused by an additional “needle”, a shallow (~0.2 eV) and narrow (<0.1 eV), defect state near the conduction band minimum (CBM). This is also discussed in terms of the dual current path caused by leakage current in the channel edge.
Highlights
Amorphous InGaZnO (a-IGZO) is a promising material in high performance displays owing to its high field-effect-mobility and extremely low leakage current compared to those of the conventional amorphous silicon (a-Si:H) thin film transistors (TFTs)
The device bias-stress stability is reported to be better for etch-stop layer (ESL) TFTs compared to that for back channel etch (BCE) TFTs, the BCE configuration is preferred to the ESL structure in the industry because it allows saving two mask photo-steps
The second cause of hump appearance is the pulsed high voltage bias stress applied at the drain electrode, which is similar in character to the gate drive integrated circuit[26] in display devices
Summary
Amorphous InGaZnO (a-IGZO) is a promising material in high performance displays owing to its high field-effect-mobility and extremely low leakage current compared to those of the conventional amorphous silicon (a-Si:H) thin film transistors (TFTs). The driving long-term stability in the oxide semiconductor has been studied from various perspectives: charge trapping[4], defect creation[5], ambient effect[6], impact ionization[3], and hot carrier injection[7] Among these causes, the common phenomenon observed is the “hump” characteristic in the current–voltage (I–V)[8,9,10] or capacitance–voltage (C–V)[11] measurement. The hump phenomena, which occur under the driving test including a positive gate bias stress test with temperature[16] or illumination[8,17], were interpreted as the back-channel conduction[14], formation of the defects[15], edge effects[18], or parasitic TFTs12,19. The hump caused by a dual current path from the channel edge current was discussed through 3D simulation of the device
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