Analysis of the Electron Traps at the 4H-SiC/SiO<sub>2</sub> Interface of a Gate Oxide Obtained by Wet Oxidation of a Nitrogen Pre-Implanted Layer

Abstract

This work is focusing on the effect of a high concentration of nitrogen (N) introduced by ion implantation at the SiO2/4H-SiC interface in MOS capacitors. The N implanted sample (Ninterface ~1x1019cm-3) is compared with a non-implanted one (Ninterface ~1x1016cm-3) by means of the electron interface trap density (Dit). The Dit is determined via High-Low frequency C-V method and Thermal Dielectric Relaxation Current (TDRC) technique. It is shown that the TDRC method, mainly used so far for determination of near interface oxide charges, can be exploited to gain information about the Dit too. The determined value of Dit in the N-implanted sample is nearly one order of magnitude lower than that in the sample without N implantation. Good agreement between the TDRC results and those obtained from High-Low frequency C-V measurements is obtained. Furthermore, the TDRC method shows a high accuracy and resolution of Dit evaluation in the region close to the majority carrier band edge and gives information about the traps located into the oxide.