Analysis of the Digital System Simulation Levels for its Design Debugging

Abstract

A brief analysis of the digital system design debugging is given, typical errors and inaccuracies of digital system designs at the development stage are listed. The levels of digital system design simulation are considered: simulation models at the level of queuing; register transfer level models; architecture and microarchitecture level models; quasi-timing logic diagram level models; models taking into account the spread of block delays. For each level of simulation, estimates of complexity and time costs are given, as well as the types of detected design errors.