Analysis of the conditions for worst case switching activity in integrated circuits

Abstract

Relentless advances in IC technologies have fueled steady increases on fabricated component density and work frequencies. As feature sizes decrease to nanometer scales, an increase in switching activity per unit of area and time is observed. When extreme switching activity occurs in a small region of an integrated circuit, malfunctions may be caused either as a consequence of a decrease in bias levels in the power grid caused by IR-drop, or due to unexpected gates output glitching caused by ground bounce. For proper circuit verification, both conditions have to be estimated and accounted for. In this paper we propose and compare methods for the identification of the conditions leading to extreme situations of switching activity in integrated circuits. Based on the results obtained we propose a method to determining the exact conditions for worst case switching activity in small areas of a circuit and in small intervals of time.