Analysis of Synchronizer, Data Loss and Occurrence of Metastability

Abstract

The many applications consist of multiple clock domains. There is data transfer between these clock domain systems. Due to different frequencies between sender and receiver there is data loss. Synchronizer is used for data synchronization. Synchronizer is having non-zero probability of failure in Globally Asynchronous Locally synchronous System on Chip. Synchronizer plays very crucial role in determining the reliability of system. The synchronizer is having parameters. These parameters associated with synchronizer are clock, data rate and timing window (setup and hold time). But in practice the synchronizer suffers from metastability as data changes in timing window due to which synchronizer failure occurs. As the metastability occurs we cannot predict the correct level of output. Metastability states are common in digital circuits, and synchronizers are must to protect their fatal effects. Originally, they were required when reading an asynchronous input. Now, with multiple clock domains on the same chip, synchronizers are required when on-chip data crosses the clock domain boundaries. The proposed architecture is modeled with verilog and simulated with Xilinx ISE design suit 13.1 and Quartus II 10.1. Analog behavior is studied by using Tanner 13.1. The probability of failure is analyzed and simulated. It has been found that it is affected by clock rate.