Analysis of switching characteristics of the digital hybrid PLL frequency synthesizer

Abstract

We address the switching characteristics of the digital hybrid phase-locked loop (DH-PLL) frequency synthesizer. We analyze the effects of the division ratio for frequency synthesis and the component errors of a DH-PLL circuit on the switching performance. Gain variation, offset error generated in a digital-to-analog converter, and frequency drift error of voltage-controlled oscillation due to temperature and aging are considered as the errors of the circuit components. From the simulation results, the conventional charge-pump PLL system has much different switching time for the change spacing of the frequency synthesis. On the contrary, the variation of the switching time is not so great in the DH-PLL system when the error magnitude does not exceed the /spl plusmn/4 least significant bit error. To guarantee the required minimum switching speed, it is important that the tolerable error range be determined.