Analysis of surface contamination on organosilicate low k dielectric materials

Abstract

It has been widely acknowledged that copper and low k dielectric materials are required in order to reduce RC delay and achieve high-speed operations in VLSI technology. Introduction of copper resulted in the adoption of damascene processing and via-first dual damascene architecture is one of the most popular integration schemes. However, photoresist poisoning is a major challenge and surface contamination of the via side-wall is considered to be the root cause. Wet cleaning has been found to be one of the processes which can lead to wafer surface contamination. In this paper, thermal desorption GC–MS and ToF-SIMS are used to analyze the surfaces of an organosilicate low k material before and after wet cleaning. It has been found that cleaning of the low k wafer with the wet chemicals used in post-etch polymer stripping process and storage of cleaned wafers in a polymer wafer box will lead to amine contamination on the low k surface, probably via airborne molecular contamination. The amount of amine contamination depends on the wet chemicals used, wafer patterning and the wafer storage conditions. The effect of amine contamination on photoresist poisoning is also discussed.