Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing

Abstract

An analysis of timing and input-referred offset of sense amplifiers (SA) is presented, and a new SA architecture with capacitive offset correction is proposed. Offset sources are first analyzed in a cross-coupled latch-based SA design, and the analysis is then extended to the proposed SA. The results show the proposed offset correction technique can reduce the total sensing time by up to 40%, while eliminating dynamic offset due to the difference in resolving inverters trip points. A self-timed SRAM with a new replica timing structure is designed to generate optimal SA enable timing with respect to the total input-referred offset. Calculations for timing delay and offset are compared with simulation results in both a conventional and a proposed SA design. The presented simulation results are based on a 10 Kb CMOS SRAM array in 130 nm BiCMOS SiGe technology operating at a 500 MHz clock and 1.5 V supply.