Analysis of silicon via hole drilling for wafer level chip stacking by UV laser

Abstract

For stacking wafers/dies, through-silicon-vias (TSVs) need to be created for electrical connection of each wafer/die, which enables better electrical characteristics and less footprints. And for via hole processing, chemical methods such as DRIE (Deep Reactive Ion Etching) are mostly used. These methods suffer the problems of slow processing speed, being environment-unfriendly and damage on the existing electric circuits due to high process temperature. Furthermore, masks are also needed. To find an alternative to the methods, researches on the laser drilling of via holes on silicon wafer are being conducted. This paper investigates the silicon via hole drilling process using laser beam. The percussion drilling method is used for this investigation. It is also examined how the laser parameters- laser power, pulse frequency, the number of laser pulses and the diameter of laser beam- have an influence on the drilling depth, the hole diameter and the quality of via holes. From these results, laser drilling process is optimized. The via hole made by UV laser on the crystal silicon wafer is 100µm deep, has the diameter of 27.2µm on the top, 12.9µm at the bottom. These diameters deviate from the target values by 2.8µm and 0.4µm respectively. These values correspond to the deviation from the target taper angle of the via hole by less than 1°. The processing speed of the laser via hole drilling is 114mm/sec, therefore, etching process can be replaced by this method, if the number of via holes on a wafer is smaller than 470,588. The ablation threshold fluence of silicon is also determined by a FEM model and is verified by experiment.