Analysis of Signals Pre-processing Algorithm in Case οf Hardware and Software Implementation οn Diagnostic Programmable Device PUD-2

Abstract

In the paper, two-stage signal pre-processing algorithm based on the ltration is presented. The developed algorithm is dedicated for the diagnostic programmable device PUD-2. The PUD-2 is the real-time analyzer based on programmable logic devices FPGA, as well as on ARM processor. Application of FPGA programmable devices and ARM processors allows to merge advantages of hardware and software implementations. Further, analysis of digital lters parameters in case of its e cient realization on the FPGA is presented. The aim of the study is to select digitallter parameters in such way that the available resources of FPGA are used e ciently and lter characteristics meet established criteria. In the study, low pass nite impulse response and in nite impulse response lters are compared. For the rst stage of the signal pre-processing algorithm, hardware implementation of the in nite impulse response lter is proposed, contrary to the second stage, where software realization of the nite impulse response lter is suggested. Combination of hardware and software ltration algorithms allows for fast and e cient realization of signal pre-processing algorithm used in analysis carried out on the PUD-2.