Abstract
In this paper, the Self-Heating Effects in Vertical FETs(VFET) have been investigated according to device geometry. It is demonstrated that the temperature of the device increases by using a low-k dielectric and an air gap between the metal lines. In addition, when air spacers are used, the lattice temperature is further increased and the on current reduction ratio increases compared to the common spacer. Also, to release the thermal bottleneck to the substrate side, the metal pad size was adjusted and the composition of the Shallow Trench Isolation (SII) was changed.
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