Analysis of RISC performance in real‐time system

Abstract

AbstractThe author has already proposed a method of analyzing the average instruction execution time for estimating the performance of CISC in a real‐time system (RTS) [1]. However, in [1] there was no mention of a method of analyzing the execution time when the CPU has a cache memory and an RISC architecture.This paper presents a simulation method for solving that problem, and clarifies the relative processing power of the two architectures. The new method converts actual RTS CISC trace data in an RTS to RISC access state data and uses the data for input in simulations of cache operation, etc., to clarify the processing performance ratio between CISC and RISC in an RTS.The results clarify that the 1‐level write‐through cache strategy (MIPS R3000) suffers from continuous writing, the two‐level write‐back cache strategy (MIPS R4000) depends strongly on the speed of the secondary cache, and that the overall RTS characteristics differ from the characteristics of application programs in a time‐sharing system (TSS), etc.These techniques go beyond simply allowing the comparison of RISC and CISC performance. They also make it possible to clarify the factors of the performance characteristics of systems that include caches on the basis of an overall software model for actual RTS.