Analysis of Power Delivery Network (PDN) in Bridge-Chips for 2.5-D Heterogeneous Integration

Abstract

In this article, we investigate the impact of power delivery network (PDN) in bridge-chip-based 2.5/3-D heterogeneous integration platforms. The focus of the article is bridge-chip-based central processing unit (CPU)-field-programmable gate array (FPGA) and FPGA-stacked memory integration technologies. While bridge-chip-based interconnect platforms present PDN challenges, depending on the power map, including a PDN in the bridge-chip can help reduce the impact significantly. We perform three case studies: 1) inclusion of ground network in the bridge-chip; 2) inclusion of power and ground network in the bridge-chip; and 3) inclusion of metal-insulator-metal (MIM) decoupling capacitors in the bridge-chip. Inclusion of both power and ground network can reduce DC IR drop by ~20% for a CPU-FPGA integration case study and by ~40% for an FPGA-stacked memory configuration. Our <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L (di/dt)$ </tex-math></inline-formula> noise analysis shows that if we include decoupling capacitors in the bridge-chip, we can significantly reduce the high-frequency ripple in the power supply. We also perform a design space exploration for power delivery with the following parameters: 1) resistance of the PDN in the bridge-chip; 2) decoupling capacitor density in the bridge-chip; and 3) overlap region between a bridge-chip and active dice.