Analysis of power consumption in a simple embedded data path unit

Abstract

An experimental 8 bit data path consisting of an ALU and 4-register register file is implemented in a 1.2 /spl mu/m CMOS process. The data path features AND and OR operations that are implemented as wired-or functions on precharged buses, making simultaneous masking and addition operations possible without extra hardware. Maximum operating frequency is 25 MHz, area 600 /spl mu/m/spl times/610 /spl mu/m (0.37 mm/sup 2/) and equivalent power dissipating capacitor of clocking and data buses is about 30 pF which corresponds to 30 pF/1700 transistors=18 fF per transistor using a 5 V supply.