Analysis of Parasitic Effects in AIGaN/GaN HEMTs

Abstract

AlGaN/GaN high electron mobility transistors (HEMTs) are now receiving great attention because of their potential applications to high-power and high-frequency devices (Mishra et al., 2008). An output power of more than 32 W/mm is reported at 4 GHz for the 0.55 μm gate-length device (Wu et al., 2004), and a current-gain cutoff frequency (fT) of 163 GHz is obtained for 0.06 μm gate length (Higashiwaki et al., 2006). However, slow current transients are often observed even if the gate voltage or the drain voltage is changed abruptly (Binari et al., 2002). This is called gate lag or drain lag, and is problematic in circuit applications. The slow transients indicate that the dc current-voltage (I-V) curves and the RF I-V curves become quite different, resulting in lower RF power available than that expected from the dc operation (Binari et al., 2002; Mishra et al., 2008). This is called power slump or current collapse. This current reduction in RF I-V curves or pulsed I-V curves is also referred to as current slump, RF dispersion and knee-walkout behavior. These parasitic effects are serious problems, and there are many experimental works reported on these phenomena (Khan et al., 1994; Daumiller et al., 2001; Ventury et al., 2001; Koley et al., 2003; Mizutani et al., 2003; Koudymov et al., 2003; Meneghesso et al., 2004; Desmaris et al., 2006), but, only a few theoretical works are reported recently (Braga et al., 2004; Meneghesso et al., 2004; Tirado et al., 2007). The literature suggests that the surface properties (surface states) play an important role in these phenomena, but traps in a buffer layer could also affect the characteristics (Binari et al., 2002; Desmaris et al., 2006). It is also shown that the gate lag and current collapse can be reduced by introducing a field plate (Koudymov et al., 2005). This is considered due to a decrease in surface-state effects. It is well recognized that the field plate can improve the breakdown voltage and the power performance, because the electric field at the drain edge of the gate is reduced (Karmalkar & Mishra, 2001; Ando et al., 2003; Xing et al., 2004; Saito et al., 2005; Pala et al., 2008). However, it is not well understood whether the field plate affects buffer-related lag phenomena and current collapse. In the previous theoretical works by device simulation, effects of a donor-type surface state (near the valence band) on gate lag and pulsed I-V curves of AlGaN/GaN HEMTs were studied (Meneghesso et al., 2004; Tirado et al., 2007), and a bulk deep-acceptor effect (~ 1 eV) above the midgap of GaN was studied for the gate lag (Braga et al., 2004). However, the types of traps and their energy levels seem to be artificial. Therefore, in this article, we have 4