Analysis of Non-Uniform Current Distribution in Multi-Fingered and Low-Voltage-Triggered LVTSCR

Zijie Zhou,Yang Wang,Peng Dong,Xiangliang Jin,Jun Luo,Yan Peng

doi:10.5755/j02.eie.25352

Zijie Zhou, Yang Wang + Show 4 more

Open Access

https://doi.org/10.5755/j02.eie.25352

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Abstract

Laterally Diffused Metal Oxide Semiconductor Silicon-Controlled Rectifier (LDMOS-SCR) is usually used in Electrostatic Discharge (ESD) protection. LDMOS-SCR discharges current by parasitic SCR, but the MOS in it cannot work when parasitic SCR is stabilized. To further enhance the Electrostatic Discharge (ESD) discharging capability of LDMOS-SCR, a novel high failure current LDMOS-SCR with 12 V operation voltage is fabricated and verified in a 0.18-um high-voltage Bipolar-CMOS-DMOS (BCD) process. Compared with conventional LDMOS-SCR, the novel LDMOS-SCR (LDMOS-SCR-R) introduced a heavily doped p-type region, which is located between the heavily doped n-type and p-type regions of Cathode and is connected with the gate. The adding p-well resistance can drop the voltage on the gate, and the gate with p-well resistance also has resistance and capacitance coupling effect. According to the results of the transmission line pulse test (TLP), the voltage applied to the gate by increasing the p-well resistance plays a major role in the device working mechanism. Under the same device size, LDMOS-SCR-R has higher It2 (8.6 A) than conventional LDMOS (2.21 A) or LDMOS-SCR (6.62 A) in TLP results. Compared with LDMOS-SCR, the failure current of LDMOS-SCR-R increases by 30 %, and the FOM of LDMOS-SCR-R increases by 34 %. The response of LDMOS-SCR-R is also faster than that of LDMOS-SCR under larger current conditions. In addition, the phenomenon in TLP results is consistent with simulation results. The proposed LDMOS-SCR-R can effectively increase failure current without affecting the device’s design window, and the additional p-type region will not increase the layout area.

Highlights

Electrostatic discharge (ESD) is very common in chip production, transportation, and testing [1]
When the applied Electrostatic Discharge (ESD) voltage is greater than the breakdown voltage of the reverse PN junction, the avalanche breakdown current flowing through Rpw will turn on the parasitic NPN and a current discharge path[1] will appear
After a transmission line pulse (TLP) pulse, the leakage current will be tested under 12 V working voltage

Summary

INTRODUCTION

Electrostatic discharge (ESD) is very common in chip production, transportation, and testing [1]. Under ESD stress, the parasitic Bipolar Junction Transistor (BJT) inside the LDMOS turns on and the embedded SCR can work to snapback region stably, the LDMOS-SCR can get higher robustness than the LDMOS device stand-alone. The authors in [20] proposed a structure, which keeps LDMOS stable in the high-current holding region after snapback for improving ESD robustness [21], [22]. Chen et al [23] proposed a LDMOS-SCR with SUPER-JUNCTION structure, which needs an additional layout mask. The authors in [24] discuss the change of failure current caused by the change of LDMOS-SCR structure size, and the. A novel design is proposed, which can increase the failure current of the LDMOS-SCR device without affecting the design window or increasing the additional mask cost. The proposed LDMOS-SCR can meet the application of 12 V operation voltage, and it has a human body model (HBM) of up to 10 kV to achieve electrostatic discharge robustness

ASYMMETRICAL LDMOS-SCR ESD PROTECTION DEVICE

EXPERIMENTAL RESULTS AND DISCUSSION

CONCLUSIONS