Analysis of non‐ideal effects in coupled VLSI interconnects with active and passive load variations

Abstract

PurposeThe aim of this paper is to analyze the effects of aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of a coupled VLSI‐interconnect system.Design/methodology/approachSignal delay, power dissipation and crosstalk noise in interconnect can be influenced by variation in load of another interconnect which is coupled to it. For active gate and passive capacitive load variations, such effects are studied through SPICE simulations of a coupled interconnect pair in a 0.13 μm technology. Crosstalk between a coupled pair, is affected by transition time of the coupled signal, interconnect length, distance between interconnects, size of driver and receiver, pattern of input, direction of flow of signal and clock skew. In this work, influence of an aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of delay, power consumption and crosstalk in a victim‐line of a coupled VLSI‐interconnect system are determined through SPICE simulation. In this experiment, the victim line is terminated by a fixed capacitive load and the coupled to aggressor line has variable load, either passive capacitive or active gate. Four different input signal cases have been considered for the two types of variable load. Distributed RLC transmission model of interconnect is considered for the SPICE simulations.FindingsThe simulation results reveal that the effects are much dependent on the type of load and signal variations at the inputs of the two mutually coupled interconnects. Load control at the aggressor far end can be used to minimize some of the adverse effects of crosstalk.Originality/valueThis paper shows that in interconnect, signal delay, power consumption and crosstalk are all affected by load variations in a coupled neighboring interconnect.