Abstract
An 18 μm thin crystalline silicon solar cell was demonstrated, and its best open circuit voltage is 642.3 mV. However, this value is far from the cell’s theoretical upper limit in an ideal case. This paper explores the open circuit voltage losses of the thin silicon solar cell, starting from the ideal case, through first principle calculation and experiments. The open circuit voltage losses come from the introduced recombination due to the non-ideal surface passivation and contacts integration on front and rear surfaces, and edge isolation. This paper presents a roadmap of the open circuit voltage reduction from an ideal case of 767.0 mV to the best measured value of 642.3 mV.
Highlights
The theoretical upper limit performance of both thick silicon solar cells [1] and thin silicon solar cells [2,3] have been well studied
An 18 μm thin crystalline silicon solar cell on steel has achieved a best efficiency of 16.8% and a best open circuit voltage (Voc) of 642.3 mV [5]
The ultrathin silicon is 20 μm thick, which is attached onto 125 μm steel substrate, and includes three layers: top front surface field (FSF) layer which is n+ and 1 μm, middle base layer, which is n type and 18 μm, and bottom emitter which is p+ 1 μm
Summary
The theoretical upper limit performance of both thick silicon solar cells [1] and thin silicon solar cells [2,3] have been well studied. The ultrathin silicon is 20 μm thick, which is attached onto 125 μm steel substrate, and includes three layers: top front surface field (FSF) layer which is n+ and 1 μm, middle base layer, which is n type and 18 μm, and bottom emitter which is p+ 1 μm. Both surfaces of this thin silicon are well passivated and optically designed. Based on our previous analysis, bulk recombination is negligible for such thin crystalline silicon solar cells [5]; it is not discussed in this paper. The Voc loss at each step is figured out and a roadmap of Voc reduction from the no loss (or modeled) case of 767 mV to the best measured value of 642.3 mV is established
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