Abstract
The retention characteristic of memory devices is an important issue as the size of the chip is scaled down continuously. However, it is hard to retain the reliable retention characteristic at smaller size of chip since the interference and leakage problems are induced by scaling down the chip. This paper suggests the main leakage mechanisms of 2x-nm flash memory at the pre-cycling situation by comparing the measurement Vth data with TCAD simulation to analyze this problem. Based on the results, we identify the failure mechanisms and factors which affect degradation of intrinsic retention characteristics.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
