Abstract
Multipliers are becoming one of the most important basic building blocks in RISC (Reduced Instruction Set Computing), Digital Signal Processor (DSP), graphics accelerators and so on. The speed performance of the multiplier often affects the overall speed performance of a VLSI system. The proposed Dadda tree multiplier (8×8) is used to reduce the computation in the multiplier partial product by the use of skiansky tree adder in the final stage of addition instead of ripple carry adder. In this paper the speed is increased by 33.3% (latency) than the conventional Wallace tree multiplier and 21% than the conventional dadda tree multiplier. This multiplier circuit is stimulated by tanner tool using 350nm technology.
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