Abstract
High frame rate imaging for applications such as meteorological forecast, motion target tracking require high-speed Read-Out Integrated Circuit (ROIC). In order to achieve 10 KHz of frame rate, this paper analyzes the bandwidth of Capacitive-feedback Trans-Impedance Amplifier (CTIA) in ROIC which is the dominant bandwidth-limiting node when interfaced with large InGaAs detector pixel capacitance of about 10pF. A small-signal model is presented to study the relationship between integration capacitance, detector capacitance, transconductance and CTIA bandwidth. Calculation and simulation results show explicitly how the series resistance at the interface restricts the frame rate of Focal Plane Arrays (FPA). In order to achieve low-noise performance at a high frame rate, this paper describes an optimal solution in ROIC design. A prototype ROIC chip (DL7) has been fabricated with 0.5-μm mixed signal CMOS process and interfaced with InGaAs detector arrays. Test results show that frame rate is above 10 KHz and ROIC noise is around 270 e<sup>-</sup>, near identical to the design value.
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