Abstract
Presents a general analysis for the calculation of harmonic distortion in single-channel monolithic analog MOS integrated circuits. Power series expressions are obtained for basic stages often used in an analog MOS technology. These include the depletion load inverter, enhancement load inverter, depletion load source follower, enhancement load source follower, and the differential pair. From the power series expressions, the second-order harmonic distortion is calculated. These results are compared with data obtained from a test chip.
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